1. Field of the Invention
The present invention relates to a multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit capable of ensuring high reliability and suppressing sub-threshold leakage current.
2. Discussion of Related Art
Semiconductor transistor devices can be classified into low threshold transistors and high threshold transistors according to threshold voltage. A low threshold transistor has a guaranteed high response speed even at low supply voltage, but consumes a large amount of power due to sub-threshold leakage current. In contrast, a high threshold transistor has a small leakage current and thus consumes little power, but shows deteriorated characteristics, such as a low response speed, at low supply voltage. When a latch or flip-flop is implemented by the low threshold transistor, sub-threshold leakage current may cause the loss of internal information of the latch or flip-flop, i.e., stored data.
The present era in the art is referred to as the deep sub-micron (DSM) era because the gate length of a semiconductor transistor has been reduced to less than 0.1 micron. In the DSM era, high power consumption due to sub-threshold leakage current is a major concern. As the gate length of a transistor is shortened and the threshold voltage is lowered, sub-threshold leakage current increases in proportion to the exponential of a voltage difference between a drain and source. Therefore, in the DSM era, a new sequential circuit structure that can prevent loss of power and/or data caused by sub-threshold leakage current is extremely important.
In the DSM era, a multi-threshold CMOS (MTCMOS) structure, MTCMOS being a power gating technique, and a variable threshold CMOS (VTCMOS) structure performing back bias voltage control are widely used as structures reducing sub-threshold leakage current.
FIG. 1 is a block diagram of a conventional MTCMOS circuit, which comprises a low threshold circuit block consisting of low threshold transistors or gates, and high threshold transistors P1 and N1 connected to a supply voltage terminal VCC and a ground voltage terminal GND. In normal operation, a sleep signal SLEEP is “low.” In a sleep mode, the sleep signal SLEEP becomes “high,” and the transistors P1 and N1 both are turned off. Thus, the transistors P1 and N1 are floated from the supply voltage terminal VCC and ground voltage terminal GND, and go into a virtual supply voltage state and a virtual ground voltage state.
FIG. 1 shows a structure controlling power supply of the circuit block consisting of low threshold transistor devices by the high threshold transistors to suppress leakage current. In the structure, the power line of the conventional MTCMOS circuit block is floated from normal voltage, and then shifts back to a normal state. Therefore, power line bounce may occur, and the total area increases because of the high threshold transistors for power gating.
FIG. 2 is a circuit diagram of a conventional VTCMOS device. A transistor illustrated in FIG. 2 is a low threshold transistor that adjusts a threshold voltage by controlling a back bias voltage and thus can reduce leakage current. Therefore, it is possible to efficiently reduce leakage current by substituting the transistor of FIG. 2 for each low threshold transistor included in a circuit block inside a chip. However, a process of fabricating a structure for applying a back bias voltage in a circuit block is complicated, an additional back bias voltage generator circuit is required, and a body factor makes it hard to control threshold voltage as the structure is scaled down.